Phase-locked loop (PLL) devices are control systems that generate signals having a fixed relationship to the phase of a reference signal. Typically, a phase-locked loop device generates a desired signal in response to both the frequency and the phase of the reference signal as well as a control signal. Often this includes raising or lowering the frequency of a frequency generator, such as a digitally controlled oscillator (DCO), a voltage controlled oscillator (VCO), or the like, until a true or modified form (a fraction, for example) of the oscillator output signal is matched with the reference signal in both frequency and phase. Phase-locked loops are widely used in radio, telecommunications, computers, and other electronic applications.
Phase and/or frequency detectors can be used with PLL devices to provide phase frequency information for controlling and tuning a frequency of the generated output signal. However, time delays in detecting the phase/frequency information or in transmitting the information to control portions of the PLL can create disturbances to the PLL clock. For example, misalignment due to a time delay can create reference spurs and increased phase noise of the clock, leading to increased jitter, or variations in the timing of the rising and/or falling edges of the periodic signal. Accumulated jitter can increase in-band phase noise, and in a worst-case scenario, misalignment can lead to unlock of the PLL.